Simulation of the classical analog phase-locked loop based circuits
نویسندگان
چکیده
منابع مشابه
Phase Locked Loop Circuits
1. Definition. A PLL is a feedback system that includes a VCO, phase detector, and low pass filter within its loop. Its purpose is to force the VCO to replicate and track the frequency and phase at the input when in lock. The PLL is a control system allowing one oscillator to track with another. It is possible to have a phase offset between input and output, but when locked, the frequencies mus...
متن کاملSimulation Of Acquisition Behavior Of Second-Order Analog Phase-Locked Loop Using Phase Error Process
This work presents a method for modeling and simulating a second-order analog phase-locked loops (PLL) in time domain for studying its acquisition behavior. The proposed method uses phase error process for analyzing the PLL characteristics. The method enables to study the lockin and pull-in phenomena of analog PLL and the effects of changing phase offset and voltage offset values on acquisition...
متن کاملA Combinational Approach of Modeling Analog Phase Locked Loop
In this paper a vital component of communication system, a general purpose analog Phase lock loop (PLL) is modeled using a novel combinational approach which apart from having a high speed also mimics IC behavior in Silicon. An analog/digital circuit simulator PSpice is used for the purpose. The advantage of SPICE is that it offers models that accurately define a CMOS process. Since, SPICE simu...
متن کاملOptimization of Phase-Locked Loop Circuits via Geometric Programming
We describe the global optimization of phaselocked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a , CMOS process. Silicon measurements show good agreement with the model. The results include a PLL with a period jitter of ...
متن کاملHigh Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IFAC-PapersOnLine
سال: 2015
ISSN: 2405-8963
DOI: 10.1016/j.ifacol.2015.05.217